The present invention relates to a thin film forming apparatus and, more particularly, to a thin film forming apparatus and method for forming a flat thin film by transferring a thin film to a substrate.
Thin film forming methods associated with electronic components can be roughly classified into sputtering, chemical vapor deposition, deposition, coating, plating, and the like. When a substrate for thin film formation has a small area, any one of the above methods can be selected to almost cope with a desired electronic component.
In recent years, however, the wafer size is steadily increasing from, e.g., 8 inches to 12 inches. Along with the increase in size of wafers used for the manufacture of LSIs or size of liquid crystal panels, demand for a thin film forming method suitable to large-size substrates has arisen.
In the field of multilevel interconnections in LSI manufacturing technologies, the surface of a dielectric film must be precisely planarized to realize a multilevel interconnection. Accordingly, demand not only for a technique coping with a large-size substrate but also for a planarization technique in thin film formation is increasing.
The followings have been examined as representative planarization techniques.
(1) SOG (Spin-On-Glass) or PIQ method (K. Sato, S. Harada, A. Saiki, T. Kitamura, T. Okubo, and K. Mukai, "A Novel Planar Multilevel Interconnection Technology Utilizing Polyimide", IEEE Trans. Part Hybrid Package., PHP-9, 176 (1973))
(2) Etch back method (P. Elikins, K. Reinhardt, and R. Layer, "A Planarization Process for Double Metal CMOS Using Spin-on Glass as a Sacrificial Layer", Proceeding of 3rd International IEEE VMIC Conf., 100 (1986))
(3) Lift off method (K. Ehara, T. Morimoto, S. Muramoto, and S. Mastuo, "Planar Interconnection Technology for LSI Fabrication Utilizing Lift-off Process", J. Electrochem. Soc., Vol. 131, No. 2, 419 (1984))
However, the SOG method utilizes the fluidity of a film and therefore can hardly realize perfect planarization.
The etch back method is the most popular technique. However, dust produced upon simultaneously etching a resist and a dielectric film is difficult to manage.
The lift off method has not been put into practice yet because the controllability or yield is insufficient due to a problem that, e.g., a stencil used cannot be completely dissolved and lifted off.
As a simple planarization technique, a bias-sputter method was proposed by C. Y. Ting et al. in 1978 (C. Y. Ting, V. J. Vivalda, and H. G. Schaefer, "Study of Planarized Sputter-Deposited-SiO.sub.2 ", J. Vac. Sci. Technol. 15, 1105 (1978)).
In addition, as a method applied to an interconnection using bias application, a bias ECR method was proposed by K. Machida et al. in 1986 (K. Machida and H. Oikawa, "SiO.sub.2 Planarization Technology with Biasing and Electron Cyclotron Resonance Plasma Deposition for Submicron Interconnections", J. Vac. Sci. Technol. B4, 818 (1986)).
In these methods, a film is formed by sputtering or ECR plasma CVD. An rf bias is applied to the substrate to cause sputtering on a substrate holder. While etching a convex region using the dependency on angle, a film is formed and planarized.
The advantages of these techniques are that a high-quality thin film can be formed even at a low temperature, and the planarization process is simple and can be easily performed.
However, they also have disadvantages such as a low throughput and damage to the device.
In 1990s, chemical mechanical polishing is proposed as a method of planarizing an interlayer dielectric (W. J. Patrick, W. L. Guthrie, C. L. Standley, P. M. Schiable, "Application of Chemical Mechanical Polishing to the Fabrication of VLSI Circuit Interconnections", J. Electrochem. Soc., Vol. 138, No. 6, June 1778 (1991)).
The chemical mechanical polishing method has received a great deal of attention because it can obtain a satisfactory planarity. However, when a dielectric film has no satisfactory characteristics, no satisfactory polishing characteristics can be obtained. Accordingly, a high-quality dielectric film must be formed at a low temperature, and polishing characteristics are unstable, resulting in disadvantages.
As described above, when any one of the prior arts is applied to a large-size semiconductor substrate, the surface planarity or uniform thin film characteristics can hardly be ensured from the viewpoint of controllability. Consequently, complicated processes must be added to cope with the large-size substrate to result in an increase in cost.